Technology

 

 CBRAM Technology

Adesto’s CBRAM Technology is the lowest power, lowest cost non-volatile memory for mainstream and embedded applications.

The non-volatile memory is created by applying patented metallization and dielectric stack layers between CMOS interconnect layers (see photo). The size of the memory cell is determined by the underlying access transistor (whether using a Logic or DRAM process). The result is a superior NVM with long-term CMOS scalability. CBRAM™ memory was originally developed at Arizona State University and is also known as Programmable Metallization Cell (PMC). It has been shown that CBRAM has the ability to operate as a low power NVM DRAM replacement. In addition, the technology has been shown to be scalable down to 12nm.

View product features

Adesto has successfully integrated CBRAM in several CMOS technology logic processes Whitepapers.

Whitepapers

We conclude that Adesto’s technology provides a real opportunity to extend DRAM-like performance into the growing market for low-power mobile applications.  
 
Convergent Semiconductors
 
 
 

For more information on CBRAM technology, please refer to the following list of selected CBRAM technical papers.

 

Journal Articles

  • "Nanoscale Memory Elements Based on Solid-Electrolytes" by M. N. Kozicki, et al / published in IEEE Trans. on Nanotechnology, vol. 4, 2005, p. 331.
  • "Nanoionic-based Resistive Switching Memories" by R. Waser, et al / published in Nature of Materials, vol. 6, 2007, p. 833.
  • "Study of Multilevel Programming in Programmable Metallization Cell (PMC) Memory", by U. Russo et al/published in IEEE Trans. on Electron Devices, vol. 56, 2009, p. 1040.
  • “Power and energy perspectives of nonvolatile memory technologies,” N. Derhacobian, S.C. Hollmer, N. Gilbert, and M.N. Kozicki, Proc. IEEE 98, 283 (2010).
  • “Inherent diode isolation in programmable metallization cell resistive memory elements,” S.C. Puthenthermadam, D.K. Schroder, and M.N. Kozicki, Applied Physics A: Materials Science & Processing 102, 4817 (2011).
  • “One-dimensional model of the programming kinetics of conductive-bridge memory cells,” J.R. Jameson, N. Gilbert, F. Koushan, J. Saenz, J. Wang, S. Hollmer, and M.N. Kozicki, Applied Physics Letters 99, 063506 (2011).
  • “Quantized conductance in Ag/GeS2/W conductive-bridge memory cells,” J.R. Jameson, N. Gilbert, F. Koushan, J. Saenz, J. Wang, S. Hollmer, M.N. Kozicki, and N. Derhacobian, IEEE Electron Device Letters 33, 257 (2012).
  • "A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control" by S. Dietrich, et al / published in IEEE J. of Solid State Circuits, vol. 42, 2007, p. 839.
  • "An Embeddable Multilevel-Cell Solid Electrolyte Memory Array" by N. Gilbert, et al / published in IEEE J. of Solid State Circuits, vol. 42, 2007, p. 1383.
  • "Redox-Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges" by R. Waser, et al / published in Advanced Material, vol. 21, 2009, p. 2632.
  • “Demonstration of conductive bridging random access memory (CBRAM) in logic CMOS process,” C. Gopalan, Y. Ma, T. Gallo, J. Wang, E. Runnion, J. Saenz, F. Koushan, P. Blanchard, and S. Hollmer, Solid-State Electronics 58, 54 (2011).
  • “Low voltage cycling of programmable metallization cell memory devices,” D. Kamalanathan, A. Akhavan, and M.N. Kozicki, Nanotechnology 22, 254017 (2011).
  • “Electrochemical metallization memories - fundamentals, applications, prospects,” I. Valov, R. Waser, J.R. Jameson, and M.N. Kozicki, Nanotechnology 22, 254003 (2011).
  • “Effects of cooperative ionic motion on programming kinetics of conductive-bridge memory cells,” J.R. Jameson, N. Gilbert, F. Koushan, J. Saenz, J. Wang, S. Hollmer, and M.N. Kozicki, Applied Physics Letters 100, 023505 (2012).
 

Conference Proceedings

  • "A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications," Nad Gilbert, Yanqing Zhang, John Dinh, Benton Calhoun, Shane Hollmer, Symposia on VLSI Technology and Circuits, Kyoto, Japan, (2013).
  • “Demonstration of conductive bridging random access memory (CBRAM) in logic CMOS process,” C. Gopalan, Y. Ma, T. Gallo, J. Wang, E. Runnion, J. Saenz, F. Koushan, and S. Hollmer, Proc. 2010 2nd IEEE Int. Memory Workshop (IMW), 50 (2010).
  • “CBDRAM: Conductive bridge dynamic RAM for DRAM replacement – repeatability & speed studies,” M.G. Ertosun, M. Kellam, B. Haukness, S. Bowyer, G. Bronner, F. Koushan, C. Gopalan, J.R. Jameson, J. Saenz, W.-T. Lee, S. Hollmer, J. Wang, and M.N. Kozicki, submitted to VLSI 2012.
  • “A high performance and low power logic CMOS compatible embedded 1Mb CBRAM non-volatile macro,” S. Hollmer, N. Gilbert, J. Dinh, D. Lewis, and N. Derhacobian, Proc. 2011 3rd IEEE International Memory Workshop (IMW), 107 (2011).
 

Invited Talks

  • “Demonstration of a sub 1 volt CMOS compatible ultra low energy non-volatile memory technology for use in discrete of embedded applications,” N. Derhacobian, S. Hollmer, and N. Gilbert, GOMACTech-10 Microelectronics for Net Enabled and Cyber Transformational Technologies, Reno, NV, March 22-25, 2010.
  • “Physics and modeling of the time required to program CBRAM cells,” J.R. Jameson, N. Gilbert, F. Koushan, J. Saenz, J. Wang, S. Hollmer, and N. Derhacobian, 1st International Workshop On Conductive Bridge Memory (CBRAM), Stanford, CA, April 23-24, 2010.
  • “Introduction to CBRAM,” M.N. Kozicki, Non-volatile Memory Conference, Santa Clara, CA, September 22, 2010.
  • “Moore’s Law and the end of scaling: Can electrochemistry put us back on track?” T. Gallo and J.R. Jameson, 3rd Annual Workshop on Electrochemistry, University of Texas, Austin, TX, Feb. 18-20, 2011.
  • “Atoms to go… Ionic Memory and Data Storage,” (keynote) M.N. Kozicki, IEEE Workshop on Microelectronics and Electron Devices, Boise, ID, April 22, 2011.
  • “Cation-based resistive memory,” M.N. Kozicki, 4th IEEE International Nanoelectronics Conference, Tao-Yuan, Taiwan, June 21-24, 2011.
  • “Physics of CBRAM cells,” J.R. Jameson, 1st International Workshop on Resistive RAM, Imec, Leuven, Belgium, Oct. 20-21, 2011.
  • “Conductive bridging RAM: Scalable, low power and high performance ReRAM technology platform,” M. Van Buskirk, New Non-Volatile Memory Workshop 2011, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, Nov. 10-11, 2011.
  • “Physics of Ag/GeS2/W conductive-bridge memory cells (CBRAM),” J.R. Jameson, Monthly meeting of the Thin Film Users Group, Northern California Chapter of the American Vacuum Society, Santa Clara, CA, Dec. 14, 2011.
  • “Integration of CBRAM in aluminum and copper logic CMOS processes,” C. Gopalan, J. Wang, Y. Ma, P. Blanchard, E. Runnion, J. Saenz, F. Koushan, T. Gallo, and S. Hollmer, 1st International Workshop On Conductive Bridge Memory (CBRAM), Stanford, CA, April 23-24, 2010.
  • “Overview of Cation-Based Resistive Memory,” M.N. Kozicki, Advances in Nonvolatile Memory Materials and Devices, Suzhou, China, July 11-16, 2010.
  • “Cation Memory Mechanisms,” M.N. Kozicki, 2010 ITRS Memory Materials Workshop, Tsukuba, Japan, November 30, 2010.
  • “Scaling of conductive-bridge memory (CBRAM): Where are we now, and how far can we go?” J.R. Jameson, IEEE Bay Area Nanotechnology Council Symposium, Santa Clara, CA, March 15, 2011.
  • “Ionic memory,” M.N. Kozicki, 1st International Workshop on RRAM, IMEC, Leuven, Belgium, October 20-21, 2011.
  • “Ionic Memory,” M.N. Kozicki, Workshop on Current Status and Future Directions of Non-Volatile Memory Technology, IEEE Santa Clara Valley Electron Devices Society, November 4, 2011.
  • “CBRAM: New opportunities through high density, low power novel embedded NVM technology,” P. Blanchard, C. Gopalan, J. Shields, W. Lee, Y. Ma, S. Park, B. Buichet, S. Hsu, T. Gallo, F. Koushan, J. Saenz, D. Wang, V. McCaffrey, C. Chen, V. Gopinath, E. Runnion, V. Gopalakrishnan, M.N. Kozicki, J. Wang, and S. Hollmer, Leading Edge Embedded NVM Workshop, Centre Microélectronique de Provence - Georges Charpak, Gardanne, France, Nov. 17, 2011.
  • “Conductive bridging RAM (CBRAM): A scalable, low power and high performance resistive memory technology platform,” M. Van Buskirk, 2012 IEEE International Interconnect Technology Conferece (IITC), San Jose, CA, June 4-6, 2012.
 

Contributed Talks

  • “Demonstration of conductive bridging random access memory (CBRAM) in logic CMOS process,” C. Gopalan, Y. Ma, T. Gallo, J. Wang, E. Runnion, J. Saenz, F. Koushan, and S. Hollmer, 2010 2nd IEEE International Memory Workshop (IMW), Seoul, Korea, May 16-19, 2010.
  • “CBDRAM: Conductive bridge dynamic RAM for DRAM replacement – repeatability & speed studies,” M.G. Ertosun, M. Kellam, B. Haukness, S. Bowyer, G. Bronner, F. Koushan, C. Gopalan, J.R. Jameson, J. Saenz, W.-T. Lee, S. Hollmer, J. Wang, and M.N. Kozicki, submitted to VLSI 2012.
  • “A high performance and low power logic CMOS compatible embedded 1Mb CBRAM non-volatile macro,” S. Hollmer, N. Gilbert, J. Dinh, D. Lewis, and N. Derhacobian, 2011 3rd IEEE International Memory Workshop (IMW), Monterey, CA, May 22-25, 2011.
 

Panel Sessions

  • N. Derhacobian, 1st International Workshop On Conductive Bridge Memory (CBRAM), Stanford, CA, April 23-24, 2010.
  • I. Naveh, TOTAL RECALL: Advanced memory technologies panel 2012, Applied Materials-Applied Ventures, Santa Clara, CA, Feb. 1, 2012.
  • N. Derhacobian, 1st International Workshop on Resistive RAM, Imec, Leuven, Belgium, Oct. 20-21, 2011.