The CBRAM cell consists of 2 non-critical layers added to the base CMOS layers all without compromising the Silicon IP.

 

Adesto’s CBRAM operating at just 1V eliminates the high voltage overhead of Flash and EEPROM and as a result can continue to follow Moore’s Law scaling. In the 64Mb device example above, the floating gate based memory size is nearly 2X larger than the device based on Adesto’s technology.

CBRAM Technology

Adesto’s CBRAM Technology is the lowest power, lowest cost non-volatile memory for mainstream and embedded applications. The non-volatile memory is created by applying patented metallization and dielectric stack layers to a standard CMOS process at the Back End of the Line (BEOL) (see photo). The size of the memory cell is determined by the underlying (Logic or DRAM) transistor. The result is a superior NVM with long-term CMOS scalability.  CBRAM was originally developed at Arizona State University and is also known as Programmable Metallization Cell (PMC).  Several semiconductor companies have developed CBRAM prototype chips that demonstrate the ability to operate as a low power NVM DRAM replacement.  In addition, the technology has been shown to be scalable down to 12nm.

For more information on CBRAM technology, please refer to the following list of selected CBRAM technical papers.