November 15, 2019 | Denise Rael
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Several classes of embedded applications require large amounts of memory for executing either code or data. For example, some connected IoT nodes use wireless networking protocols that have large software stacks, while embedded AI and machine learning applications require large data sets. In each case, these applications require more memory storage than will economically fit on a standard embedded chip.
Introducing Execute in Place (XiP), a system architecture that enables the execution of code directly from external serial flash memory, which can be as large as necessary to meet application requirements. However, standard serial flash devices (as used for BIOS, etc.) are not optimal for code execution because of their relatively slow access speed (throughput), high latency and power consumption. To enable XiP, the flash memory must be specifically designed for high performance while maintaining the power efficiency of serial memory.
To meet these needs, Adesto designed EcoXiP™ Octal xSPI non-volatile memory to serve as external memory that is able to meet the performance requirements of XiP architectures. This memory device takes advantage of advances in serial interfaces, architectural enhancements and power-efficient implementation to meet the performance demands.
XiP increases design flexibility, as it allows the use of MCUs without internal flash memory, or with limited on-chip memory, to handle high performance processing.
To design EcoXiP, Adesto had to overcome numerous technical challenges to transform basic serial flash memory into an energy-efficient external memory device that can act as high-performance random-access memory in XiP architectures. Three of the most significant challenges were performance, power efficiency and software updates.
Challenge #1: Performance bottlenecks
The processor and external flash memory are connected via a serial peripheral interface (SPI), limiting the bandwidth available for code and data accesses.
To address this, EcoXiP uses a multi-line, smart serial peripheral interface. This is compliant with JESD251, JEDEC’s latest standard for Octal extended SPI (xSPI). The standard also defines the use of double data rate (DDR), where data is transferred on both clock edges, to provide an extra doubling of data throughput. Lastly, the standard adds a data-strobe signal which enables higher bus frequency while transferring data at a dual data rate.
The combination of these techniques increases the available bandwidth by a factor of more than 4 when compared with standard quad SPI memory devices.
In addition, the interface supports a special wrap-and-continue read command, which reduces the latency of fetching missing cache lines. When using this command, a series of instruction fetches can be fused into a single bus operation, eliminating the need for incurring the latency of separate commands for each instruction fetch.
Challenge #2: Power efficiency
Driving signals between chips is one of the main contributors to system power consumption. The serial interface helps to mitigate this by minimizing the number of pins used for address and data signals.
EcoXiP uses further energy optimization techniques to offer competitive power usage in XiP mode, with read current of 35mA typical, about half that of similar Octal SPI devices.
It also provides deep power-down and ultra-deep power-down modes, drawing as little as 200 nanoamps. This is particularly valuable in portable and hand-held devices, where battery life is critical, and systems are regularly put into standby mode when not being used.
Challenge #3: Over-the-air updates
Keeping software up to date is vital, particularly for connected systems where there is a risk that security vulnerabilities in firmware could be exploited by malware.
The challenge here is that the write speed of normal flash memory is orders of magnitude slower than read speed. This means that writing to the flash can block read requests for an extended period of time, resulting in processing deadlock.
Adesto’s EcoXiP flexibly partitions the flash memory to enable concurrent read and write accesses, known as read-while-write (RWW) mode. The host processor can continue reading from one partition while simultaneously modifying data in another.
This means that over-the-air (OTA) updates can be supported. While code is being executed from one partition, the new code is downloaded and written to the “spare” partition. Once the update is complete the software can be verified, using a checksum or cryptographic signature, and the execution is switched to the new partition. The previous code partition is available as a fall-back, in case there are problems with the update, and for future updates.
RWW mode is also useful for periodic data logging and other data storage uses. One partition can be used for code execution, another can be allocated for a potential OTA update and a third one could be used for writing logged data.