Mixed Signal Circuit Design Engineer
Adesto Technologies is looking for a Mixed Signal Circuit Design Engineer to join our Mixed signal and Non-volatile memory design team as an Analog/Mixed-signal Design engineer focused on NVM memory design and full chip integration.
Responsibilities Will Include But Are Not Limited To
– Design and simulate Bandgap reference voltage, LDO (low drop out voltage regulator), high voltage charge pump (both positive and negative ), memory Read/Write paths
– Work with Design and Layout teams to create floorplan, signal routing strategy, signal routing methodology and power grid design for a mixed signal chip design. Many routes are sensitive analog signals and special high voltage paths, so this is a semi-custom routing process.
– Construct wire models and simulations for pre-layout estimation of supply droops and critical signal analysis.
– Work with layout and design to mitigate issues with signal and power grid integrity.
– Work with the design team on full chip mixed signal simulation strategy and execution, post layout simulation and analysis of results.
– Help integrate reliability tool flows into pre-silicon simulation methodology.
– Cross team interface skills along with good written and oral communication skills are very important.
Prior years of experience with the skillsets below
– Design Experience with Flash NOR or PCM or RRAM non-volatile memory design with strong fundamentals in Flash-cell/Semiconductor device physics, transistor level analog/mixed signal & I/O circuit design.
– Experience with CMOS digital, analog, and I/O circuit design.
– Experience in product life cycle – from definition to design to pre/post-silicon validation to product qualification.
– 5+ years of experience in UNIX and programming C++, Perl, TCL, Python.
– Experience with transistor-level circuit simulation tools SPICE5+ years of experience in transistor and semiconductor device layout methods.
– Experience using custom design environments such as Cadence Virtuoso.
– Experience in DRC, LVS, and post-layout extraction tools.
– Experience with timing closure and constraint files
– Minimum 10 years of Design experience
– BS degree in Electrical Engineering, Computer Engineering or a related discipline. An MSEE or MSCE degree is preferred.